Many conventional FeRAM devices include a horizontal ferrocapacitor structure in which a stack of layers is formed including top and bottom electrodes sandwiching a ferroelectric layer. An alternative vertical capacitor structure was suggested in U.S. Pat. No. 6,300,652 the disclosure of which is incorporated herein by reference. A vertical capacitor includes a ferroelectric element sandwiched between electrodes all at substantially the same level in the FeRAM device.
The structure of a conventional vertical capacitor is shown in FIG. 1. The vertical capacitors are typically formed over a substructure, which may for example be of the form shown in FIG. 1 in which various electronic components 1 are connected to conductive plugs 3 which extend upwards through an interlayer dielectric layer such as a matrix 5 of, for example TEOS (tetraethylorthosilicate). The upper ends of the plugs 3 terminate in titanium nitride/iridium barrier elements 7 having a top surface flush with the surface of the matrix 5.
An insulating layer 9 of aluminium oxide is formed over the surface of the matrix 5 and a thicker layer of ferroelectric material 11 such as PZT (PbZrTiO3) is formed over the insulating layer 9.
Hard mask elements are deposited over selected areas of the PZT layer 11 and the portions of the PZT 11 and the aluminium oxide 9 which are not protected by the hard mask elements are etched all the way through forming openings.
The openings are then filled with conductive material 19 such as iridium oxide (IrO2) by depositing iridium oxide over the entire structure and chemical mechanical planarization polishing (CMP) is performed to form a flat upper surface which is partly PZT 11 and partly the conductive material 19. Then an aluminium oxide layer 23 is formed over the surface. The elements 19 of conductive material constitute electrodes whilst the remaining PZT 11 forms the dielectric.
The vertical capacitor structure has advantages in that it reduces the cell size and is easy to connect. The main difficulties are in reducing the height of the capacitors and etching the ferroelectric layers vertically, both of which make it difficult to reduce the size of the cell and achieve a high aspect ratio for the capacitor.
In view of the foregoing problems with conventional processes and devices, a need exists for an easily applied method for producing capacitors with a high aspect ratio and enabling etching of ferroelectric layers vertically, without reducing production yield or compromising performance.